The invention relates to reducing clock skew.
As shown in FIGS. 1 and 2, in a computer system 10, a reference clock circuit 104 located in a base computer unit 100 is typically used to synchronize operations of a synchronous circuit 106 located in the base computer unit 100 with operations of a synchronous circuit 152 located in a remote computer unit 150. The reference clock circuit 104 furnishes a clock signal CLOCKA to a clock line 108 of a cable 130 extending between the base computer unit 100 and the remote computer unit 150. A clock signal, CLOCKB, received by the synchronous circuit 152 from the clock line 108 is skewed, or delayed, relative to the clock signal CLOCKA, by a propagation delay time t.sub.pd.
Signals received and furnished by the synchronous circuit 152 are synchronized with the clock signal CLOCKB. If a clocked signal CLOCKED.sub.-- SIGNAL1 is provided by the synchronous circuit 152 and transmitted over a signal line 110 of the cable 130, a corresponding clocked signal CLOCKED.sub.-- SIGNAL2 received by the synchronous circuit 106 from the signal line 110 is delayed by two propagation delay times (2.multidot.t.sub.pd) relative to the clock signal CLOCKA.
In order to compensate for the propagation delay time t.sub.pd, an active or passive delay element is typically inserted in the clock line 108 of the cable 130 to increase the propagation delay so that the clock signals CLOCKA and CLOCKB are exactly an integral number of clock periods apart. The clock signals CLOCKA and CLOCKB then appear in phase. If either the frequency of the reference clock circuit 104 or the length of the cable 130 changes, then the delay element must be re-tuned.